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| (R) STV8162 - STV8162D +5 V, +5 V and +8 V Triple-Voltage Regulator with Disable and Reset Functions DATASHEET Key Features Input Voltage range between 7 V and 18 V Output Currents up to 600 mA Fixed Precision Output 1 voltage of 5 V 2% Fixed Precision Output 2 voltage of 5 V 2% Fixed Precision Output 3 voltage of 8 V 2% Output 1 with Reset facility Outputs 2 and 3 can be disabled by digital input Short Circuit Protection on each output Thermal Protection Low Dropout Voltages Clipwatt 11 Order Code: STV8162 DESCRIPTION The STV8162 and STV8162D are monolithic triple positive voltage regulators designed to provide three fixed precision output voltages of 5 V, 5 V and 8 V for currents up to 0.6 A. An internal reset circuit generates a reset pulse when the voltage of Output 1 drops below the regulated voltage value. Outputs 2 and 3 can be disabled by a digital input. Short-circuit and thermal protections are included in all versions. Power DIP 18 (9 + 9) Order Code: STV8162D GROUND GROUND GROUND GROUND GROUND GROUND GROUND GROUND GROUND 10 11 12 13 14 15 16 17 18 9 8 7 6 5 4 3 2 1 DISABLE INPUT3 OUTPUT3 INPUT2 OUTPUT2 INPUT1 OUTPUT1 DELAY CAPACITOR RESET Top View 11 10 9 8 7 6 5 4 3 2 1 NC DISABLE INPUT3 OUTPUT3 INPUT2 GROUND OUTPUT2 INPUT1 OUTPUT1 DELAY CAPACITOR RESET February 2004 1/12 GENERAL INFORMATION STV8162 - STV8162D 1 GENERAL INFORMATION Figure 1: STV8162 Block Diagram DELAY CAPACITOR 2 1 Reference RESET INPUT1 4 Regulator 1 Protections 3 OUTPUT1 INPUT2 7 Regulator 2 5 OUTPUT2 INPUT3 9 DISABLE 10 Regulator 3 8 OUTPUT3 11 Not Connected 6 GROUND Figure 2: STV8162D Block Diagram DELAY CAPACITOR 2 1 Reference RESET INPUT1 4 Regulator 1 Protections 3 OUTPUT1 INPUT2 6 Regulator 2 5 OUTPUT2 INPUT3 8 DISABLE 9 Regulator 3 7 OUTPUT3 GROUND Pins 10 to 18 2/12 STV8162 - STV8162D Electrical Characteristics 2 2.1 Electrical Characteristics Absolute Maximum Ratings Parameter DC Input Voltage at pins INPUT1, INPUT2 and INPUT3 Disable Input Voltage at pin DISABLE Output Voltage at pin RESET Output Currents Power Dissipation Storage Temperature Junction Temperature Symbol VIN VDIS VRST IOUTPUT Pt TSTG TJ Value 20 20 20 Internally Limited Internally Limited -65 to +150 0 to +150 Unit V V V C C 2.2 Thermal Data Parameter Junction-to-Case Thermal Resistance Junction-to-Ambient Thermal Resistance 1 Maximum Recommended Junction Temperature Operating Free Air Temperature Range STV8162 STV8162D STV8162 STV8162D Symbol RthJC RthJA TJ TOPER Value 3 15 10 56 140 0 to +70 Unit C/W C/W C C 1. Mounted on board. For more information, refer to Section 5. 2.3 Electrical Characteristics TAMB = 25 C, VIN1 = 7 V, VIN2 = 7 V and VIN3 = 10 V, unless otherwise specified. Symbol VOUT1 VOUT2 VOUT3 VOUT1 Parameter Output Voltage Output Voltage Output Voltage Output Voltage Test Conditions IOUT1 = 10 mA IOUT2 = 10 mA IOUT3 = 10 mA 7 V < VIN1 < 12 V 5 mA < IOUT1 < 600 mA 7 V < VIN2 < 12 V 5 mA < IOUT2 < 600 mA 10 V < VIN3 < 15 V 5 mA < IOUT3 < 600 mA Min. 4.90 4.90 7.84 4.80 Typ. 5.00 5.00 8.00 Max. 5.10 5.10 8.16 5.20 Unit V V V V VOUT2 Output Voltage 4.80 5.20 V VOUT3 Output Voltage 7.68 8.32 V 3/12 Electrical Characteristics STV8162 - STV8162D Symbol VIO1 VIO2 VIO3 VOUT1LI Parameter Dropout Voltage Dropout Voltage Dropout Voltage Line Regulation Test Conditions IOUT1 = 0.6 A IOUT2 = 0.6 A IOUT3 = 0.6 A 7 V < VIN1 < 12 V, IOUT1 = 200 mA 7 V < VIN2 < 12 V, IOUT2 = 200 mA 10 V < VIN3 < 15 V, IOUT3 = 200 mA 5 mA < IOUT1 < 600 mA 5 mA < IOUT2 < 600 mA 5 mA < IOUT3 < 600 mA IOUT1 = 10 mA Outputs 2 and 3 disabled K = VOUT1 See circuit description. Ce = 100 nF See circuit description. IRESET = 5 mA VRESET = 10 V TJ = 0 to 125C Min. Typ. 1 1 1 Max. 1.4 1.4 1.4 50 Unit V V V mV VOUT2LI Line Regulation 50 mV VOUT3LI VOUT1LO VOUT2LO VOUT3LO IQ VO1RST VRTH tRD VRL IRH KOUT1 KOUT2 KOUT3 IOUT1SC IOUT2SC IOUT3SC VDISH VDISL IDIS TJSD TSDH Line Regulation Load Regulation Load Regulation Load Regulation Quiescent Current Reset Threshold Voltage Reset Threshold Hysteresis Reset Pulse Delay Saturation Voltage in Reset Condition Leakage Current in Normal Condition, at RESET pin 80 100 100 160 2.2 K-0.4 30 K-0.25 75 25 3.0 K-0.10 120 mV mV mV mV mA V mV ms 0.4 10 V mA Output Voltage Thermal Drift DVOUT x 10 K OUT = ------------------------------DT x V OUT VIN1 = 7 V VIN1 = 7 V VIN3 = 10 V 6 100 ppm/C Short Circuit Output Current Short Circuit Output Current Short Circuit Output Current 0.8 0.8 0.8 2 1.3 1.3 1.3 1.8 1.8 1.8 A A A V Voltage High Level at DISABLE pin (Outputs 2 and 3 active) Voltage Low Level at DISABLE pin (Outputs 2 and 3 disabled) Bias Current at DISABLE pin 0 V < VDISABLE < 7 V 0.8 -100 150 15 2 V mA C C Junction Temperature for Thermal Shutdown Thermal Shutdown Temperature Hysteresis 4/12 STV8162 - STV8162D Circuit Description 3 Circuit Description The STV8162 and STV8162D are triple-voltage regulators with Reset and Disable functions. The three regulation parts are supplied from a single voltage reference circuit trimmed by zener zapping during EWS testing. Since the supply voltage of this voltage reference is connected to pin INPUT1 (VIN1), the second and third regulators will not work if pin INPUT1 is not supplied. The output stages are designed using a Darlington configuration with a typical dropout voltage of 1.0 V. IMPORTANT: In all applications, all three inputs must be polarized. If Outputs 2 or 3 are not used, the corresponding inputs must be connected to Input 1. The Disable circuit will switch off pins OUTPUT2 and OUTPUT3 if a voltage less than 0.8 V is applied to pin DISABLE. The Reset circuit checks the voltage at pin OUTPUT1. If this voltage drops below VOUT1-0.25 V (4.75 V Typ.), the "a" comparator (Figure 3) rapidly discharges the external capacitor (Ce) and the reset output immediately switches to low. When the voltage at pin OUTPUT1 exceeds VOUT1-0.175 V (4.825 V Typ.), the VCe voltage increases linearly to the reference voltage (VREF = 2.5 V) corresponding to a Reset Pulse Delay (tRD) as shown in Figure 4. C e 2.5V tRD = ------------------------10mA Afterwards, the reset output returns to high. To avoid glitches in the reset output, the second comparator "b" has a large hysteresis (1.9 V). 5/12 Application Diagrams STV8162 - STV8162D 4 Application Diagrams Figure 3: Reset Diagram 10 A VREF OUTPUT1 REG VREF = 2.5 V +a 3 Ce VREF 0.6V + b RESET Figure 4: Internal Reset Voltage VOUT1 K VO1RST VRTH RESET K = Actual Value of VOUT1 tRD Power On tRD Power Off 6/12 STV8162 - STV8162D Figure 5: STV8162 Typical Application Application Diagrams C1 to C6 = 10 F Ce 1 RESET 0.1 F 2 DELAY CAPACITOR OUTPUT1 3 OUTPUT2 5 OUTPUT3 8 VIN1 VIN2 VIN3 C1 C2 C3 4 INPUT1 7 INPUT2 9 INPUT3 VOUT1 VOUT2 VOUT3 C4 C5 C6 GROUND DISABLE 6 10 NC 11 Figure 6: STV8162D Typical Application C1 to C6 = 10 F Ce 1 RESET 0.1 F 2 DELAY CAPACITOR OUTPUT1 3 OUTPUT2 5 OUTPUT3 7 VIN1 VIN2 VIN3 C1 C2 C3 4 INPUT1 6 INPUT2 8 INPUT3 VOUT1 VOUT2 VOUT3 C4 C5 C6 GROUND DISABLE 9 Pins 10 to 18 7/12 Power Dissipation and Layout Indications STV8162 - STV8162D 5 Power Dissipation and Layout Indications The power is mainly dissipated by the three device buffers. It can be calculated by the equation: P = (VIN1-VOUT1) x IOUT1 + (VIN2-VOUT2) x IOUT2 + (VIN3-VOUT3) x IOUT3 The following table lists the different RthJA values of these packages with or without a heat sink and the corresponding maximum power dissipation assuming: Maximum Ambient Temperature = 70 C Maximum Junction Temperature = 140 C Device STV8162 Yes No STV8162D Yes 32 2.2 15 56 to 40 4.6 1.25 to 1.75 Heat Sink No RthJA in C/W 50 PMAX in W 1.4 Figure 7: Thermal Resistance (Junction-to-Ambient) of DIP18 Package without Heat Sink 60 RthJA C/W 55 50 45 40 To optimize the thermal conductivity of the copper layer and the exchanges with the air, the solder must cover the maximum amount of this area. Test Board with "On Board" square heat sink area. 6 0 2 4 8 10 12 Copper area (cm) (35 m plus solder) Board is face-down Figure 8: Metal plate mounted near the STV8162D for heat sinking Top View Bottom View 8/12 STV8162 - STV8162D Package Mechanical Data 6 Package Mechanical Data Figure 9: 11-pin Plastic Clipwatt Package C A H1 H3 L E F M1 M G1 G D mm Dim. Min. A B C D E F G H1 H2 H3 L L1 L2 L3 M M1 N 10.70 19.85 17.90 14.45 11.00 5.50 2.54 2.54 Number of Pins 11 11.20 0.421 0.49 0.80 1.57 1.70 12.00 18.60 0.781 0.15 1.50 0.55 0.91 1.83 0.019 0.031 0.062 L1 B L2 Inches Max. 3.20 1.05 0.006 0.059 0.002 0.036 0.067 0.480 0.732 0.700 0.569 0.433 0.217 0.100 0.100 0.441 0.072 Typ. Min. Typ. Max. 0.126 0.041 9/12 Package Mechanical Data Figure 10: 18-pin Plastic Dual In-line Power Package STV8162 - STV8162D E A2 A1 A L b D1 b3 D b2 e eB c 18 10 E1 1 9 mm Dim. Min. A A1 A2 b b2 b3 c D D1 e eB E E1 L 7.62 6.10 2.92 7.87 6.35 3.30 0.38 2.92 0.36 1.14 0.76 0.20 22.35 0.13 2.54 10.92 8.26 7.11 3.81 0.300 0.240 0.115 3.30 0.46 1.52 0.99 0.25 22.86 4.95 0.56 1.78 1.14 0.36 23.37 Inches Max. 5.33 0.015 0.115 0.014 0.045 0.030 0.008 0.880 0.005 0.100 0.430 0.310 0.250 0.130 0.325 0.280 0.150 0.130 0.018 0.060 0.039 0.010 0.900 0.195 0.022 0.070 0.045 0.014 0.920 Typ. Min. Typ. Max. 0.210 10/12 STV8162 - STV8162D Revision History 7 Revision History Table 1: Summary of Modifications Version 0.2 0.3 Date January 2000 November 2002 First Edition Addition of PDIP18 package. Main Changes 11/12 Revision History NOTES: STV8162 - STV8162D Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics All other names are the property of their respective owners (c) 2004 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States www.st.com 12/12 |
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